consumption. However, a critical part is the wide-band AFE of the transmitter. Since there is
no analog narrow-band filter matched to the channel bandwidth, the linearity of the building
blocks, e.g. the power-amplifier, is a crucial figure.
6.1.3 Implementation Issues
In order to implement as many functionalities as possible in the digital domain and thus
provide a means for adapting the radio to different air interfaces, the sample rates at the
analog/digital interface are chosen very high. In fact, they are chosen as high as the ADC and
DAC allow. The algorithms realizing the functionalities of the DFE must be performed at
these high sample rates. As an example, digital down-conversion should be mentioned. As
can be seen in Section 6.3, a digital image rejection mixer requires four real multiplications
per complex signal sample. Assuming a sample rate of 100 million samples per second
(MSps) this yields a multiplication rate of 400 million multiplications per second. This
would occupy a good deal of the processing power of a DSP, however, without really
requiring its flexiblity. Therefore it is not sensible to realize digital down-conversion on a
digital signal processor. The same consideration also holds in principle for channelization and
sample-rate conversion: very high sample rates in connection with signals of high dynamic
range makes the application of digital signal processors questionable. If, moreover, the signal
processing algorithms do not require much flexiblity from the underlying hardware platform
it is not sensible to use a DSP.
A solution to this problem is parameterizable and reconfigurable hardware. Reconfigurable
hardware is hardware whose building blocks can be reconfigured on demand. Field program-
mable gate arrays (FPGAs) belong to this class. Up to now these FPGAs have a long
reconfiguration time compared to the processing speed they offer. Therefore they cannot
be reconfigured dynamically, i.e. while processing. On the other hand, the application in
mobile communications systems is well defined. There is a limited number of algorithms that
must be realized. For that reason hardware structures have been developed that are not as fine-
grained as FPGAs. This means that the building blocks are not as general as in FPGAs but are
much more tailored to the application. This results in reduced effort.
If the granularity of the hardware platform is made even more coarse, the hardware is no
longer reconfigurable but parameterizable. Dedicated building blocks whose functionality is
fixed can be implemented on application specific integrated circuits (ASICs) very efficiently. If
the main parameters are tunable, these ASICs can be employed in software defined radio
transceivers. A simple example is the above-mentioned digital down-conversion. The only
thing that must be tunable is the frequency of the local oscillator. Besides this, the complete
underlying hardware does not need to be changed. This is very efficient as long as digital down-
conversion is required. In a potential operation mode not requiring digital down-conversion of
a software radio, the dedicated hardware block cannot be used and must be regarded as ballast.
However, with respect to the wide-band signal at the output of the analog-to-digital
converter in a digital receiver, it is sensible to assume that the functionalities of the DFE,
namely channelization and sample-rate conversion, are necessary for most air interfaces.
Hence, the idea of dedicated parameterizable hardware blocks promises to be an efficient
solution. Therefore, all considerations and investigations in this chapter are made with respect
to an implementation as reconfigurable hardware.
Hardware and implementation issues are covered in detail in subsequent chapters.
The Digital Front End – Bridge Between RF and Baseband Processing 155
6.2 The Digital Front End
6.2.1 Functionalities of the Digital Front End
From the previous section it can be concluded that the functionalities of the DFE in a receiver
are
† channelization (i.e. down-conversion and filtering), and
† sample-rate conversion.
The functionalities of a receiver DFE are illustrated in Figure 6.4. It should be noted that the
order of the three building blocks (digital down-conversion, SRC, and filtering) is not neces-
sarily as shown in Figure 6.4. This will become clear in the course of the chapter.
Since the DFE should take over as many tasks as possible from the AFE in a software radio,
the functionalities of the DFE are very similar to what has been described in Section 6.1.1 for
the front end in general. The digitized wide-band signal comprises several channels among
which the channel-of-interest is centered at an arbitrary carrier frequency. Channelization is
the functionality that shifts the channel-of-interest to baseband and moreover removes all
adjacent channel interferers by means of digital filtering.
Sample rate conversion (SRC) is a relatively ‘young’ functionality in a digital receiver. In
conventional digital receivers the analog/digital interface has been clocked with a fixed rate
derived from the master clock rate of the air interface that the transceiver was designed for. In
Software Defined Radio: Enabling Technologies156
Figure 6.4 A digital receiver with a digital front end
software radio transceivers there is no isolated target air interface. Therefore the transceiver
must cope with different master clock rates. Moreover, it must be borne in mind that the
terminal and base station run mutually asynchronously and must be synchronized when the
connection is set up.
There are two approaches to overcome these two problems. First, the analog/digital inter-
face can be clocked with a tunable clock. Thus, for all air interfaces the right sampling clock
can be used. Additionally, it is possible to ‘pull’ the tunable oscillator for synchronization
purposes. It is clear that such a tunable oscillator requires considerably more effort than a
fixed one. For that reason designers favour the application of a fixed oscillator. Nonetheless,
the baseband processing requires a signal with a proper sample rate. Hence, sample-rate
conversion is necessary in this case for converting between the fixed clock rate at the
analog/digital interface and the target rate of the respective air interface.
Very often interpolation (e.g. Lagrange interpolation) is regarded as a solution to SRC.
Still, this solution is only sensible in certain applications. The usefulness of conventional
interpolation depends on the signal characteristics. In Section 6.1.1, it has been mentioned
that the wide-band signal at the input of the DFE of a receiver can comprise several channels
beside the channel-of-interest. However, only the channel-of-interest is really wanted. This
fact can be exploited for reducing the effort for SRC (see Section 6.5).
Since both channelization and SRC require filtering, it is possible to combine them. This
can lead to considerable savings. A well-known example is multirate filtering [1]. This is a
concept where filtering and integer factor SRC (e.g. decimation) are realized stepwise on a
cascaded structure comprising several stages of filtering and integer factor SRC. Generally,
this results in both a lower multiplication rate and a lower hardware complexity.
The functionalities of the transmitter part of a DFE are equivalent to those of the receiver
part: the baseband signal to be transmitted is filtered, digitally up-converted, and its sample
rate is matched to the sample rate of the analog/digital interface. Although there are no
adjacent channels to be removed, filtering is necessary for symbol forming and in order to
fulfill the spurious emissions characteristics dictated by the respective standard. Again,
filtering and SRC can be combined.
There is a strong relationship between digital down-conversion and channel filtering since
they form the functionality channelization. On the other hand, it has been mentioned that
there is also a strong relationship between channel filtering and SRC, e.g. in the case of
multirate filtering. In the main part of this chapter, a separate section is dedicated to each of
the three, digital down-conversion, channel filtering, and sample-rate conversion. Important
relations between them are dealt with in these sections.
6.2.2 The Digital Front End in Mobile Terminals and Base Stations
The great issue of mobile terminals is power consumption. Everything else is less important.
Power consumption is the alpha and the omega of mobile terminal design. On the other hand,
mobile terminals usually must only process one channel at a time. This fact enables the
application of efficient solutions for channelization and SRC that are based on the multirate
filtering concept.
In contrast to this there are no restrictions regarding power consumption in base stations
besides basic environmental aspects. Still, in base stations several channels must be processed
in parallel.
The Digital Front End – Bridge Between RF and Baseband Processing 157
This fundamental difference between mobile terminals and base stations must be kept in
mind when investigating and evaluating algorithms and potential solutions.
6.3 Digital Up- and Down-Conversion
6.3.1 Initial Thoughts
The notion of up- and down-conversion stands for a shift of a signal towards higher or lower
frequencies, respectively. This can be achieved by multiplying the signal
x
a
ðtÞ with a complex
rotating phasor which results in
x
b
ðtÞ¼x
a
ðtÞe
j2
p
f
c
t
ð1Þ
where f
c
stands for the frequency shift. Often f
c
is called the carrier frequency to which a
baseband signal is up-converted, or from which a band-pass signal is down-converted.
However, in this case f
c
would have to be positive. Regarding it as a frequency shift enables
us to use positive and negative values for f
c
.
The real and imaginary parts of a complex signal are also called the in-phase and the
quadrature-phase components, respectively.
Digital up- and down-conversion is the digital equivalent of Equation (1). This means that
both the signals and the complex phasor are represented by quantized samples (quantization
issues are not covered in this chapter). Introducing a sampling period T, that fulfills the
sampling theorem, digital up- and down-conversion can be written as
x
b
ðkTÞ¼x
a
ðkTÞe
j2
p
f
c
kT
ð2Þ
Assuming perfect analog-to-digital or digital-to-analog conversion, respectively,
Equations (1) and (2) are equivalent.
Depending on the sign of f
c
, up- or down-conversion results. Thus, it is sufficient to deal
with one of the two. Only digital down-conversion is discussed in the sequel.
It should be noted that real up- and down-conversion is also possible and indeed very
common, i.e. multiplying the signal with a sine or cosine function instead of the complex
exponential of Equations (1) and (2). However, real up- and down-conversion is a special
case of complex up- and down-conversion and is therefore not discussed separately in this
chapter.
6.3.2 Theoretical Aspects
In order to understand the task of digital down-conversion, it is useful to consider the
complete signal processing chain of up-conversion in the transmitter, transmission, and
final down-conversion in the receiver. It is assumed that the received signal is down-
converted twice. First the complete receive band is down-converted in the AFE. This is
followed by filtering. The processed signal is again down-converted in the DFE. This is
sketched in Figure 6.5.
For the discussion it is assumed that there are no distortions due to the channel, however, it
introduces adjacent channel interferers. Thus, the received signal x
Rx
ðtÞ is equal to the
transmitted signal x
Tx
ðtÞ plus adjacent channel interferers aðtÞ:
Software Defined Radio: Enabling Technologies158
x
Rx
ðtÞ¼x
Tx
ðtÞþaðtÞ
¼ Re
x
Tx;BB
ðtÞe
j2
p
f
c
t
no
þ aðtÞð3Þ
¼
1
2
x
Tx;BB
ðtÞe
j2
p
f
c
t
þ x
Ã
Tx;BB
ðtÞ e
ÿj2
p
f
c
t
þ aðtÞð4Þ
where
x
Tx;BB
ðtÞ is the complex baseband signal to be transmitted. f
c
denotes the carrier
frequency and
x
Ã
the conjugate complex of x. From Equation (4) it can be concluded that
the received signal comprises two components besides the adjacent channel interferers: one
centered at f
c
and another centered at ÿf
c
. The first comprises the signal-of-interest x
Tx;BB
ðtÞ.
It lies anywhere in the frequency band of bandwidth B which comprises several frequency
divided channels, i.e. the channel-of-interest plus adjacent channel interferers. This band is
selected by a receive band-pass filter. The arrangement of the channel-of-interest (i.e. the
signal x
Rx
ðtÞ) in the receive frequency band is sketched in Figure 6.6.
As mentioned above the analog front end performs down-conversion of the complete
receive frequency band of bandwidth B. Inside this frequency band lies the signal-of-interest
x
Tx;BB
ðtÞ which should finally be down-converted to baseband. The following signal is
produced at the output of the analog down-converter when down-converting by f
1
. For
reasons of simplicity of the derivation we shall limit f
1
to f
1
, f
c
.
x
Rx;IF
ðtÞ¼x
Rx
ðtÞe
ÿj2
p
f
1
t
ð5Þ
¼
1
2
x
Tx;BB
ðtÞ e
j2
p
ðf
c
ÿf
1
Þt
þ x
Ã
Tx;BB
ðtÞ e
ÿj2
p
ðf
c
þf
1
Þt
þ a
filt
ðtÞe
ÿj2
p
f
1
t
ð6Þ
where a
filt
ðtÞ denotes all adjacent channel interferers inside the receive bandwidth B. The
interesting signal component is centered at the intermediate frequency (IF)
The Digital Front End – Bridge Between RF and Baseband Processing 159
Figure 6.5 The signal processing chain of up-conversion, transmission, and final down-conversion of
a signal (LO stands for local oscillator)
f
IF
¼ f
c
ÿ f
1
ð7Þ
It is enclosed by several adjacent channel interferers. A second signal component lies 2f
c
apart from the first (sketched in Figure 6.7).
The latter is of no interest; moreover, it can cause aliasing in the analog-to-digital conver-
sion process. Therefore it is removed by low-pass (or band-pass) filtering. Thus, the digitized
signal is:
x
dig;IF
ðkTÞ¼
1
2
x
Tx;BB
ðkTÞe
j2
p
f
IF
kT
þ a
dig
ðkTÞð8Þ
where
a
dig
ðkTÞ stands for the remaining adjacent channels after down-conversion, anti-alias-
ing filtering, and digitization. T is the sampling period that must be small enough to fulfill the
sampling theorem. In general the digital IF signal is a complex signal; the interesting signal
component is centered at f
IF
.
The objective of digital down-conversion is to shift this interesting component from the
carrier frequency f
IF
down to baseband. By inspection of Equation (8) it can be found that
down-conversion can be achieved by multiplying the received signal with a respective expo-
nential function:
Software Defined Radio: Enabling Technologies160
Figure 6.6 Position of the channel-of-interest in the receive frequency band of bandwidth B
Figure 6.7 Position of the channel-of-interest at IF
x
dig;BB
ðkTÞ¼x
dig;IF
ðkTÞe
ÿj2
p
f
IF
kT
ð9Þ
¼
1
2
x
Tx;BB
ðkTÞþa
dig
ðkTÞe
ÿj2
p
f
IF
kT
ð10Þ
This yields a sampled version of the transmitted signal
x
Tx;BB
ðtÞ scaled with a factor 1/2. It is
sketched in Figure 6.8. The adjacent channel interferers can be removed with a channelization
filter (see Section 6.4).
It should be noted that in reality the oscillators of transmitter and receiver are not synchro-
nized. Therefore, down-conversion in the receiver yields a signal with phase offset and
frequency offset that must be corrected. The aim of the derivation in this section was to
show what happens with the signal in principle in the individual processing stages and not to
discuss all possible imperfections.
6.3.3 Implementation Aspects
In practical applications it is necessary to treat the real- and imaginary part of a complex
signal separately as two individual real signals. Thus, the signal after analog down-conver-
sion comprises the following two components:
Re
x
Rx;IF
ðtÞ
¼ Re x
Rx
ðtÞ e
ÿj2
p
f
1
t
no
¼ x
Rx
ðtÞ cos 2
p
f
1
t
ð11Þ
Im x
Rx;IF
ðtÞ
¼ Im x
Rx
ðtÞ e
ÿj2
p
f
1
t
no
¼ÿx
Rx
ðtÞ sin 2
p
f
1
t
ð12Þ
It can be concluded that analog down-conversion can be implemented by means of multi-
plying the received real signal by a cosine signal and a sine signal. The real part of the
complex IF signal (also called the in-phase component) is obtained by multiplying the
The Digital Front End – Bridge Between RF and Baseband Processing 161
Figure 6.8 Channel-of-interest at baseband (result of low-pass filtering of the signal of Figure 6.7
followed by digital down-conversion)
received signal with a cosine signal; the imaginary part of the complex IF signal (also called
the quadrature-phase component) is obtained by multiplying the received signal with a sine
signal.
From Equation (8) it can be concluded that the input signal to the digital down-converter is
in principle a complex signal. Hence, the digital down-conversion described by Equation (9)
requires a complex multiplication. Since the complex signals are only available in the form of
their real and imaginary parts, the complex multiplication of the digital down-conversion
requires four real multiplications. By separating the real and imaginary parts of Equation (9),
we have
Re
x
dig;BB
ðkTÞ
no
¼ Re x
dig;IF
ðkTÞ
no
cos 2
p
f
IF
kT
þIm
x
dig;IF
ðkTÞ
no
sin 2
p
f
IF
kT
ð13Þ
Im
x
dig;BB
ðkTÞ
no
¼ Im x
dig;IF
ðkTÞ
no
cos 2
p
f
IF
kT
ÿRe
x
dig;IF
ðkTÞ
no
sin 2
p
f
IF
kT
ð14Þ
This can be regarded as a direct implementation of digital down-conversion. It is sketched in
Figure 6.9.
There are two special cases:
1. When the signal
x
dig;IF
ðkTÞ is real, it is Im x
dig;IF
ðkTÞ
no
¼ 0. Hence, digital down-conver-
sion can be realized by means of two real multiplications in this case.
2. When applying the above results to up-conversion, it is often sufficient to keep the real part
Software Defined Radio: Enabling Technologies162
Figure 6.9 Direct realization of digital down-conversion
of the up-converted signal. Thus, only Equation (13) must be solved resulting in an effort
of two real multiplications and one addition per signal sample.
The samples of the discrete-time cosine and sine functions in Figure 6.9 are usually stored
in a look-up table. The ROM table can simply be addressed by the output signal of an
overflowing phase accumulator representing the linearly rising argument ð2
p
f
IF
kTÞ of the
cosine and sine functions. Requiring a resolution of n bits, the look-up table has a size of
approximately 2
n
 n bits which together with the four general purpose multipliers results in
large chip area, high power consumption, and considerable costs [18].
The large look-up table can be avoided by generating the samples of the digital sine and
cosine functions with an infinite length impulse response (IIR) oscillator. It is an IIR filter
with a transfer function that has a complex or conjugate complex pole on the unit circle [5].
Another way to generate the sine and cosine samples without the need for a large look-up
table is the CORDIC algorithm (CORDIC stands for COordinate Rotation Digital Computer).
The great advantage of the CORDIC algorithm is that it not only substitutes the large look-up
table but also the required four multipliers. This is possible since the CORDIC algorithm can
be used to perform a rotation of the complex phase of a complex number. Interpreting the
samples of the complex signal
x
dig;IF
ðkTÞ as these complex numbers, and rotating the phase of
these samples according to ð2
p
f
IF
kTÞ, the CORDIC algorithm directly performs the digital
up- or down-conversion without the need for explicit multipliers.
6.3.4 The CORDIC Algorithm
The CORDIC algorithm was developed by Volder [25] in 1959 for converting between
cartesian and polar coordinates. It is an iterative algorithm that solely requires shift, add,
and subtract operations. In the circular rotation mode, the CORDIC calculates the cartesian
coordinates of a vector which is rotated by an arbitrary angle.
To rotate the vector
v
0
¼ e
j
f
ð15Þ
by an angle D
f
, v
0
is multiplied by the corresponding complex rotating phasor
v ¼ v
0
·e
jD
f
ð16Þ
The real and imaginary parts of
v are calculated individually:
Re
v
fg
¼ Re v
0
fg
cosðD
f
ÞÿIm v
0
fg
sinðD
f
Þð17Þ
Im
v
fg
¼ Im v
0
fg
cosðD
f
ÞþRe v
0
fg
sinðD
f
Þð18Þ
Rearranging yields
Re v
fg
cosðD
f
Þ
¼ Re
v
0
fg
ÿ Im
v
0
fg
tanðD
f
Þ; jD
f
j Ó
1
2
p
;
3
2
p
; …
ð19Þ
Im v
fg
cosðD
f
Þ
¼ Im
v
0
fg
þ Re
v
0
fg
tanðD
f
Þ; jD
f
j Ó
1
2
p
;
3
2
p
; …
ð20Þ
The Digital Front End – Bridge Between RF and Baseband Processing 163
Note that only the tangent of the angle D
f
must be known to achieve the desired rotation. The
rotated vector is scaled by the factor 1= cosðD
f
Þ.
For many applications it is too costly to realize the two multiplications of Equations (19)
and (20). The idea of the CORDIC algorithm is to perform the desired rotation by means of
elementary rotations of decreasing size, thus iteratively approaching the exact rotation by D
f
.
By choosing the elementary rotation angles as tanðD
f
i
Þ¼^1=2
i
, the multiplications of
Equations (19) and (20) can be replaced by simple shift operations.
D
f
i
¼ ^ arctan 2
ÿi
; i ¼ 0; 1; 2; … ð21Þ
Consequently, in order to rotate a vector
v
0
by an angle D
f
¼ z
0
with jD
f
j ,
p
=2, the
CORDIC algorithm performs a sequence of successively decreasing elementary rotations
with the basic rotation angles D
f
i
¼ ^ arctanð2
ÿi
Þ for i ¼ 0; 1; …; n ÿ 1. The limitation of
D
f
is necessary to ensure uniqueness of the elementary rotation angles. Finally, the iterative
process yields the cartesian coordinates of the rotated vector
v
n
% v. The resulting iterative
process can be described by the following equations for i ¼ 0; 1; …; n ÿ 1:
x
iþ1
¼ x
i
ÿ d
i
y
i
2
ÿi
ð22Þ
y
iþ1
¼ y
i
þ d
i
x
i
2
ÿi
ð23Þ
z
iþ1
¼ z
i
ÿ d
i
arctanð2
ÿi
Þð24Þ
where
x
0
¼ Re v
0
fg
ð25Þ
y
0
¼ Im v
0
fg
ð26Þ
x
n
¼ Re v
n
fg
ð27Þ
y
n
¼ Im v
n
fg
ð28Þ
The figure
d
i
¼
ÿ1ifz
i
, 0
þ1 otherwise
ð29Þ
defines the direction of each elementary rotation. After n iterations the CORDIC iteration
results in
x
n
% A
n
x
0
cosðz
0
Þÿy
0
sinðz
0
Þ
¼ Re A
n
v
0
e
jz
0
no
ð30Þ
y
n
% A
n
y
0
cosðz
0
Þþx
0
sinðz
0
Þ
¼ Im A
n
v
0
e
jz
0
no
ð31Þ
z
n
% 0 ð32Þ
where
Software Defined Radio: Enabling Technologies164
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